1. Field of the Invention
The present invention is directed in general to data communications. In one aspect, the present invention relates to a method and system for improving descriptor based packet processing in microprocessor or multiprocessor computer devices.
2. Related Art
As is known, communication technologies that link electronic devices may route and process signal information in the networked computer and electronic systems. Where packets are used to communicate among the linked devices, each networked system must receive and transmit packets, and must process the packets directed to that system to determine what is being transmitted to that system. Some communication technologies interface a one or more processor devices for processing packet-based signals in a network of computer systems. While a device or group of devices having a large amount of memory and significant processing resources may be capable of performing a large number of tasks, significant operational difficulties exist in coordinating the operation of multiprocessors to process the packet transfer operations.
For example, in linked computer systems that include one or more interfaces or ports on which packets are transmitted and received, each interface generally includes a dedicated DMA engine used to transmit received packets to memory in the system and to read packets from the memory for transmission. If a given system includes two or more packet interfaces, the system includes DMA engines for each interface. Where a multiprocessor computer system processes multiple packet channels using the DMA engines, the processor(s) in the system must be able to efficiently process the DMA transfers for each channel by distributing the transfers amongst the processors for handling.
In conventional multiprocessor systems that use descriptors for DMA transfers, software prepares descriptors in the memory and informs the DMA engine by updating a count register by the number of descriptors it has prepared. The DMA engine reads these descriptors to execute the data transfer specified in the descriptors. When the DMA engine is done processing the descriptors, the DMA engine typically writes back to memory the first descriptor (i.e., the descriptor identifying the start of the packet to be transferred) from a sequence of one or more descriptors for a given DMA packet transfer. In such systems, the processor executing the software does not know how many descriptors are used for the packet transfer by reading the first descriptor. In addition, when only the first descriptor is written back, the processor can not snoop the other released descriptors. As a result, only one processor can work on packet processing of one channel, and therefore load balancing between several processors can not be implemented unless this processor works as a load distributor, in which case full multiprocessor functionality is not realized. Finally, conventional descriptor-based DMA transfers have a limited packet length if the maximum packet length is restricted to the length of the packet length field in the first descriptor.
Therefore, a need exists for methods and/or apparatuses for improving the processing of descriptor-based packet transfers to quickly and efficiently write packets of data to memory, and to so in a way that quickly and efficiently provides for load balancing among the processor(s). Further limitations and disadvantages of conventional systems will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the drawings and detailed description which follow.